Event driven phase noise simulation and modeling of an ADPLL by System Verilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows circuit designers to explore different ADPLL architectures at the early stage without going through the time-consuming circuit level simulation. Pure System Verilog implementation also makes it possible to simulate the phase noise effect of the ADPLL efficiently in a large SOC system.

Additional Metadata
Persistent URL dx.doi.org/10.1109/BMAS.2008.4751235
Conference 2008 IEEE International Behavioral Modeling and Simulation Workshop, BMAS 2008
Citation
Wen, T. (Tingjun), & Kwasniewski, T. (2008). Phase noise simulation and modeling of ADPLL by system verilog. Presented at the 2008 IEEE International Behavioral Modeling and Simulation Workshop, BMAS 2008. doi:10.1109/BMAS.2008.4751235