High frequency low cost CMOS LNA design procedure for the wireless industry
This paper presents a design procedure used in industry for designing low-power narrowband high-gain CMOS LNAs for wireless applications for frequencies greater than 6GHz, with considerations for process variations. This paper does not give detailed derivations of equations. Rather, it gives the simulation procedure and methodology that converges quickly to a practical optimized solution for LNA designs mostly used in mobile communication industry for mass-production, requiring minimal time and resources from the designer. It takes a wholistic design approach where all factors, including manufacturing costs, technology choice and applications are considered. It explains how to design the appropriate topology from the "grounds up" approach, and then giving the designer the option to match the ports or not, depending on if it is appropriate. This method yields these LNA parameters at 6.5GHz: S21=18dB, NFmin=3.22dB, NF=6.1dB and S22<-15dB with only 6.4mW (plus 2.5mW for narrowband output match) power consumption over 1.2V supply.
|Conference||2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC|
Ahmed, A. (Abdulhakim), & Wight, J. S. (2008). High frequency low cost CMOS LNA design procedure for the wireless industry. In 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. doi:10.1109/EDSSC.2008.4760669