2008-12-01
Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology
Publication
Publication
Presented at the
2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC (December 2008)
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doi.org/10.1109/EDSSC.2008.4760694 | |
2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC | |
Organisation | Department of Electronics |
Wang, B. (Bo), Chen, D. (Dianyong), Liao, A. (Andrea), Liang, B. (Bangli), & Kwasniewski, T. (2008). Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology. Presented at the 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC. doi:10.1109/EDSSC.2008.4760694
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