An 8Gb/s current mode logic (CML) transmitter with multi-tap FIR pre-emphasis has been implemented in 0.18μm CMOS technology and verified to operate with PRBS7 data over a 34" FR4 backplane. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. At receive side, a frequency and phase-locked clock and data recovery (CDR) circuit incorporates a multiphase voltage-controlled oscillator (VCO) and a half-rate bang-bang phase/frequency detector (PFD) with embedded data retiming. The total power dissipation of the transceiver is 75mW at a 1.8V supply.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ISCAS.2005.1464799
Conference IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Citation
Li, M. (Miao), Huang, W. (Wenjie), Kwasniewski, T, & Wang, S. (Shoujun). (2005). A 0.18μm CMOS transceiver design for high-speed backplane data communications. Presented at the IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005. doi:10.1109/ISCAS.2005.1464799