Delay modeling of CMOS/CPL logic circuits
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. In this paper, the combination of standard CMOS with CPL is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.
|Conference||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005|
Wan, Y. (Yuanzhong), & Shams, M. (2005). Delay modeling of CMOS/CPL logic circuits. Presented at the IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005. doi:10.1109/ISCAS.2005.1465910