The design of an all-digital Data Recovery (DR) circuit requires careful system-level design space exploration. The advantages of an all-digital implementation are the ease of portability and reduced time-to-market across fabrication processes and with reducing feature sizes. For a selected architecture, this paper explores the effects of sweeping the bit detection interval of a bang-bang phase detector, the phase update interval, and the number of clock phases used for data recovery using a Matlab/Simulink model. The simulation results show the variation of jitter tolerance f the DR circuit with respect to the above parameters. An all-digital architecture can be made adaptive to jitter conditions, if the design trade-offs are known a priori. A statistical graphing/analysis tool is used to present the 3D logarithmic scatter plots.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ISCAS.2005.1465628
Conference IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Citation
Ahmed, S.I., & Kwasniewski, T. (2005). An all-digital data recovery circuit optimization using matlab/simulink. Presented at the IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005. doi:10.1109/ISCAS.2005.1465628