An energy-efficient transceiver architecture for short range wireless sensor applications
A low-power, energy-efficient and configurable transceiver architecture is introduced. It is implemented on a single chip intended for use in short range radios based on WPAN (IEEE802.15.4) at 2.4GHz. The circuitry employed in the dual conversion receiver with the tunable LNA is re-used in the dual loop frequency synthesizer to form a constant envelope modulator and function as the transmitter; Techniques are presented for tuning the center frequency and bandwidth of the LNA, as well as generating the required local oscillator frequencies using injection locking mechanism. The transceiver is fabricated in a 0.18-μm standard CMOS process. The receiver achieves -83-dBm sensitivity and -25dBm 1-dB compression point. The transmitter outputs -7-dBm QPSK signal, while carrier phase noise is better than -108-dBc/Hz at 5-MHz offset. Active mode power consumption is 11-mW and 14-mW in receive and transmit modes, respectively, on a 1.6-V supply.
|2009 IEEE Radio and Wireless Symposium, RWS 2009|
|Organisation||Department of Electronics|
Yousefi, R. (Reza), & Mason, R. (2009). An energy-efficient transceiver architecture for short range wireless sensor applications. Presented at the 2009 IEEE Radio and Wireless Symposium, RWS 2009. doi:10.1109/RWS.2009.4957387