A 4GHz ADPLL-based integer-N frequency synthesizer is reported in this paper. It employs a low-complexity digital phase and frequency detector as well as a non-linear phase and frequency decision circuit to significantly reduce the hardware complexity while maintain a comparable in-lock performance to other high-complexity ADPLLs. The ADPLL was fabricated in 90nm CMOS technology to prove its feasibility. Operating with a high-frequency-resolution DCO, the proposed low-complexity ADPLL exhibits a programmable loop bandwidth from 100kHz to 6MHz with and an excellent in-band phase noise performance.

Additional Metadata
Persistent URL dx.doi.org/10.1109/CICC.2007.4405790
Conference 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Citation
Zhuang, J. (Jingcheng), Du, Q. (Qingjin), & Kwasniewski, T. (2007). A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. Presented at the 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007. doi:10.1109/CICC.2007.4405790