A 10-Gb/s CMOS sample-and-hold phase detector using dual substrate technique
This paper presents the design of a full-rate CMOS phase detector for clock and data recovery applications in Synchronous Optical Network (SONET) OC-192 systems. Comparing the phase difference of a 10-GHz clock and a 10-Gb/s data signal severely challenges the speed capability of CMOS technology. As a result, phase detectors are traditionally designed in technologies with high power consumption such as GaAs or SiGe, or half-rate phase-locked loop structures which suffer from poor jitter performance and slow settling time are used. In this paper, a sample-and-hold phase detector for 10-Gb/s Non Return Zero data implemented in a standard 0.18μm CMOS technology is presented. A new dual-substrate technique is used to overcome the small rail-to-rail supply voltage headroom available for short channel length CMOS technology. The simulation and measurement results show that linear ranges with no dead zone on phase errors from -π/2 to π/2 are achieved. The core circuit dissipates a total power of 19.2 mW from a +/-1.6 V supply.
|Clock and data recovery, Dual-substrate technique, High speed low power CMOS circuits, PLLs, Sample-and-hold phase detectors|
|Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004|
|Organisation||Department of Electronics|
Hui, Z.W.Y. (Zoe Wai Ying), & Kwasniewski, T. (2004). A 10-Gb/s CMOS sample-and-hold phase detector using dual substrate technique. Presented at the Canadian Conference on Electrical and Computer Engineering; Technology Driving Innovation, 2004. doi:10.1109/CCECE.2004.1349756