2009-10-27
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel
Publication
Publication
Presented at the
2009 Canadian Conference on Electrical and Computer Engineering, CCECE '09 (May 2009)
| Additional Metadata | |
|---|---|
| Keywords | Backplane, Band-limited channel, Decision-feedback equalizer (DFE), Equalization, ISI, SerDes, Serial link, Wireline transceiver |
| Persistent URL | dx.doi.org/10.1109/CCECE.2009.5090320 |
| Conference | 2009 Canadian Conference on Electrical and Computer Engineering, CCECE '09 |
| Citation |
Wang, B. (Bo), Chen, D. (Dianyong), Liang, B. (Bangli), Jiang, J. (Jinguang), & Kwasniewski, T. (2009). A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. Presented at the 2009 Canadian Conference on Electrical and Computer Engineering, CCECE '09. doi:10.1109/CCECE.2009.5090320
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