2009-12-01
A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application
Publication
Publication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Volume 17 - Issue 12 p. 1742- 1748
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Clock and data recovery (CDR), Digital threshold, Examining window, Jitter tolerance, Phase-locked loop (PLL) | |
dx.doi.org/10.1109/TVLSI.2009.2017794 | |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |
Organisation | Department of Electronics |
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2009). A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1742–1748. doi:10.1109/TVLSI.2009.2017794
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