Additional Metadata
Keywords Clock and data recovery (CDR), Digital threshold, Examining window, Jitter tolerance, Phase-locked loop (PLL)
Persistent URL dx.doi.org/10.1109/TVLSI.2009.2017794
Journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Citation
Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2009). A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1742–1748. doi:10.1109/TVLSI.2009.2017794