A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application

Du, Q. (Qingjin), Zhuang, J. (Jingcheng) and T. Kwasniewski (Tad)

2009-12-01

Additional Metadata
Keywords	Clock and data recovery (CDR), Digital threshold, Examining window, Jitter tolerance, Phase-locked loop (PLL)
Persistent URL	doi.org/10.1109/TVLSI.2009.2017794
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Organisation	Department of Electronics
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style American-Institute-of-Physics Style Council-of-Science-Editors Style BibTex Format Endnote Format RIS Format CSL Format DOIs only Format	Du, Q. (Qingjin), Zhuang, J. (Jingcheng), & Kwasniewski, T. (2009). A low-power, fast acquisition, data recovery circuit with digital threshold decision for SFI-5 application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1742–1748. doi:10.1109/TVLSI.2009.2017794

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