Design and implementation of a multiplierless reconfigurable DFT/DCT processor
A Multiplierless Reconfigurable DFT/DCT Processor (MRP) design suitable for multicarrier applications is presented. The MRP implementation is based on a Reconfigurable Systolic Array (RSA) architecture that supports N-point DFT or DCT computations. All multiplication blocks in the MRP circuit have been implemented using the CSE-BitSlice technique to reduce hardware usage, and power consumption. Simulation results show that the MRP DFT circuit implementations can be used in most OFDM modulation realizations required by broadband communication systems and compression schemes of major digital video standards. The reconflgurability of the MRP makes it suitable for Shape Adaptive DCT (SA-DCT) computations required by object based video coding systems.
|2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09|
|Organisation||Department of Electronics|
Ho, H., Szwarc, V., & Kwasniewski, T. (2009). Design and implementation of a multiplierless reconfigurable DFT/DCT processor. Presented at the 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. doi:10.1109/NEWCAS.2009.5290428