A parallel solver for steady state analysis of nonlinear circuits is presented. The solver uses the Message Passing Interface specification for communications and is suitable for steady state simulation of very large nonlinear circuits. Performance of the solver is investigated on symmetric multiprocessing, non-uniform memory access, and distributed memory computer systems. Impact of memory subsystem constraints on the solver efficiency is evaluated.

Additional Metadata
Keywords Distributed memory systems, Frequency domain analysis, Harmonic analysis, Jacobian matrices, Nonlinear circuits, Parallel architectures, Shared memory systems
Persistent URL dx.doi.org/10.1109/TCAD.2009.2034499
Journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Citation
Soveiko, N. (Nick), Nakhla, M.S, & Achar, R. (2010). Comparison study of performance of parallel steady state solver on different computer architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(1), 65–77. doi:10.1109/TCAD.2009.2034499