Design and optimization of edge equalizer for high-speed electrical backplane

Chen, D. (Dianyong), Wang, B. (Bo), Liang, B. (Bangli), Cheng, D. (Dezhong) and T. Kwasniewski (Tad)

2009-12-01

Presented at the 7th International Conference on Information, Communications and Signal Processing, ICICS 2009 (December 2009)

Additional Metadata
Keywords	Backplane, Duobinary, Edge equalizer, ISI, Jitter, NRZ
Persistent URL	dx.doi.org/10.1109/ICICS.2009.5397646
Conference	7th International Conference on Information, Communications and Signal Processing, ICICS 2009
Citation APA Style AAA Style APA Style Cell Style Chicago Style Harvard Style IEEE Style MLA Style Nature Style Vancouver Style BibTex Format Endnote Format RIS Format CSL Format	Chen, D. (Dianyong), Wang, B. (Bo), Liang, B. (Bangli), Cheng, D. (Dezhong), & Kwasniewski, T. (2009). Design and optimization of edge equalizer for high-speed electrical backplane. Presented at the 7th International Conference on Information, Communications and Signal Processing, ICICS 2009. doi:10.1109/ICICS.2009.5397646

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