This paper presents a unified model for delay estimation in various CMOS logic styles including conventional, DCVSL, and YI'L. It also intmduces a simple expression for MOSFET saturation current and derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits and reports the results. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area by taking advantage of the strong points in each logic style.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ICECS.2003.1301926
Conference 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003
Citation
Shams, M. (2003). A unified delay model for CMOS logic styles. Presented at the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003. doi:10.1109/ICECS.2003.1301926