Clock and data recovery (CDR) circuits using bangbang phase detectors (BBPDs) are widely used in high speed serial links. The BBPD quantizes the phase difference between the input data and the recovered clock, generating a two state output for the loop filter (LF). The two-state output causes the behavior of the BBPD to be highly nonlinear and difficult to analyze. This paper provides a detailed analysis of the jitter transfer for second order bang-bang CDR circuits. Two popular representations of the second order bang-bang CDR circuits are used for our analysis. A detailed derivation of the jitter transfer expression is presented using each representation. Then a modified expression is derived, which is then verified by a phase-domain model implemented in Simulink. Simulation results show good agreement with the derived expression.

Additional Metadata
Keywords Bang-bang, CDR, Clock and data recovery, Jitter transfer, Phase detector
Persistent URL dx.doi.org/10.1109/ICEIE.2010.5559711
Conference 2010 International Conference on Electronics and Information Engineering, ICEIE 2010
Citation
Gabr, A. (Ahmed), & Kwasniewski, T. (2010). Unifying approach for jitter transfer analysis of bang-bang CDR circuits. Presented at the 2010 International Conference on Electronics and Information Engineering, ICEIE 2010. doi:10.1109/ICEIE.2010.5559711