2010-11-05
CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique
Publication
Publication
Presented at the
2010 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010 (May 2010)
In this paper, the design of a fully-integrated CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique that allows for broadband distortion reduction is presented. Simulation results has yielded a peak S21 power gain of 7.1 dB and then rolls off to a unity gain bandwidth of 16 GHz with less than -10 dB return loss and S12 Isolation less than -45 dB. The simulation results show a 9 dBm IIP3 improvement corresponding to a third-order intermodulation IM3 suppression of 18 dB improvement at output power of -10 dBm. The proposed linearized interleaved distributed 2 × 3 matrix amplifier was designed using the 0.13μm CMOS technology.
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| doi.org/10.1109/CCECE.2010.5575149 | |
| 2010 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010 | |
| Organisation | Department of Systems and Computer Engineering |
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El-Khatib, Z. (Ziad), MacEachern, L, & Mahmoud, S.A. (2010). CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique. Presented at the 2010 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010. doi:10.1109/CCECE.2010.5575149
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