In this paper, the design of a fully-integrated CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique that allows for broadband distortion reduction is presented. Simulation results has yielded a peak S21 power gain of 7.1 dB and then rolls off to a unity gain bandwidth of 16 GHz with less than -10 dB return loss and S12 Isolation less than -45 dB. The simulation results show a 9 dBm IIP3 improvement corresponding to a third-order intermodulation IM3 suppression of 18 dB improvement at output power of -10 dBm. The proposed linearized interleaved distributed 2 × 3 matrix amplifier was designed using the 0.13μm CMOS technology.

Additional Metadata
Keywords Active post distortion and optimum gate bias linearization, CMOS distributed interleaved matrix amplifier, Third-order intermodulation distortion suppression, Ultra-wideband wireless communications
Persistent URL dx.doi.org/10.1109/CCECE.2010.5575149
Conference 2010 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010
Citation
El-Khatib, Z. (Ziad), MacEachern, L, & Mahmoud, S.A. (Samy A.). (2010). CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique. Presented at the 2010 23rd Canadian Conference on Electrical and Computer Engineering, CCECE 2010. doi:10.1109/CCECE.2010.5575149