A method for designing faster digital CMOS circuits operating in the subthreshold mode is proposed. Since the threshold voltage may be lower at narrower widths owing to the inverse-narrow-width effect in modern nanometre MOSFETs, the subthreshold current may be higher than expected at these narrow widths. It is shown that using only transistor widths that maximise the current-to-capacitance ratio, either individually or in parallel stacks, as appropriate, leads to faster circuits. Speed increases of up to 2.85 times have been demonstrated in ring oscillator simulations.

Additional Metadata
Persistent URL dx.doi.org/10.1049/el.2011.0141
Journal Electronics Letters
Citation
Muker, M., & Shams, M. (2011). Designing digital subthreshold CMOS circuits using parallel transistor stacks. Electronics Letters, 47(6), 372–374. doi:10.1049/el.2011.0141