We demonstrate that designing subthreshold digital circuits using only similarly-sized PMOS and similarly-sized NMOS transistors usually results in faster circuits than those scaled according to conventional design methods such as Logical Effort. This statement is valid if both transistor types exhibit the inverse narrow-width effect. For proving the claim, a number of circuits are designed in both ways, compared, and the results are reported.

Additional Metadata
Keywords CMOS, Logic design, Subthreshold circuits, VLSI
Persistent URL dx.doi.org/10.1587/elex.8.1983
Journal IEICE Electronics Express
Citation
Muker, M. (Manmit), & Shams, M. (2011). Preference of designing CMOS subthreshold logic circuits using uniform-size transistors. IEICE Electronics Express, 8(23), 1983–1988. doi:10.1587/elex.8.1983