In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.

Additional Metadata
Persistent URL dx.doi.org/10.1109/EPEPS.2011.6100232
Conference 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011
Citation
Charest, A. (Andrew), Nakhla, M.S, & Achar, R. (2011). Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems. In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS-2011 (pp. 223–226). doi:10.1109/EPEPS.2011.6100232