Over the past decade, different adiabatic logic styles for low-power applications have been published. This paper compares and analyzes the performance and energy dissipation of various adiabatic logic styles in a uniform test environment. The test benches are laid out and a test chip has been fabricated in a standard 0.18 μm CMOS technology. The results are mainly based on test chip measurements and post layout simulations.

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Persistent URL dx.doi.org/10.1109/INMIC.2004.1492971
Conference 8th International Multitopic Conference, INMIC 2004
Arsalan, M, & Shams, M. (2004). Comparative analysis of adiabatic logic styles. Presented at the 8th International Multitopic Conference, INMIC 2004. doi:10.1109/INMIC.2004.1492971