This paper presents two novel modifications to the conventional true single-phase clock (TSPC) divide-by-2 clock divider. In the first variation, the maximum frequency of operation is carefully increased beyond its normal frequency of operation. This limits the time certain nodes have to respond and causes an additional clock cycle to be skipped, resulting in division by three. Simulation results predict an increase in maximum frequency range of 2 to 3 GHz, and the robustness of this mode of operation is demonstrated in measured results. The second variation emulates this cycle skipping behavior at lower frequencies by the addition of a series switch in the discharge path of a node as well as the circuitry needed to control this switch. A total of eight additional transistors are added to turn the divide by two circuit into a variable 2/3-divider and is shown in simulation to consume up to 30% less power than a conventional variable divider.

Additional Metadata
Persistent URL dx.doi.org/10.1109/NEWCAS.2012.6329050
Conference 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Citation
Lam, J. (Jerry), & Plett, C. (2012). Modified TSPC clock dividers for higher frequency division by 3 and lower power operation. Presented at the 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. doi:10.1109/NEWCAS.2012.6329050