A gate sizing and transistor fingering strategy for subthreshold CMOS circuits
Parallel Transistor Stacks (PTS) has been shown to be an effective technique for improving the speed of digital circuits operating in the subthreshold region which comes at the cost of power consumption and area. However, our experience shows that using PTS is not beneficial in all cases. In this paper, we present a methodology to identify whether using PTS is beneficial (or not) in a particular CMOS technology and what transistor sizing can be employed to maximize the circuit speed. Our technique is based on analyzing the Current-Over- Capacitance (COC) ratio of PMOS and NMOS transistors. The results of incorporating the proposed methodology in a 4-bit comparator and a 19-stage inverter ring oscillator, using 90 nm CMOS technology, illustrate 26% and 40% extra improvement compared to the blind use of PTS, respectively.
|Keywords||CMOS, Logic design, Subthreshold circuits, VLSI|
|Journal||IEICE Electronics Express|
Nabavi, M. (Morteza), & Shams, M. (2012). A gate sizing and transistor fingering strategy for subthreshold CMOS circuits. IEICE Electronics Express, 9(19), 1550–1555. doi:10.1587/elex.9.1550