The CDR (Clock and Data Recovery) using PLL with Bang-Bang PD (Phase Detector), CP (Charge Pump), and RC (Resistor and Capacitor) filter is widely used in Serdes circuits. This paper provides a detailed analysis to Bang-Bang CDR's dynamic behaviors and jitter tolerance. Then the slewing conditions, locking condition, and jitter tolerance curve, which are verified by a model implemented in Simulink, are proposed for choosing the filter parameters when designing the circuits.

Additional Metadata
Keywords CDR, integral path, jitter tolerance, proportional path, slewing
Persistent URL dx.doi.org/10.1109/CCECE.2012.6334824
Conference 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012
Citation
He, C. (Chao), & Kwasniewski, T. (2012). Bang-Bang CDR's acquisition, locking, and jitter tolerance. Presented at the 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012. doi:10.1109/CCECE.2012.6334824