A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clock is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and can achieve small frequency step while maintaining low jitter accumulation. The frequency multiplication part is achieved by using either edge-combing DLL or MDLL structure, while the programmable injection clock is obtained by employing a DLL-based digital-to-phase converter. Based on the proposed architecture, a frequency synthesizer with 50MHz-1.3GHz output frequency tuning range has been design in 0.18μm CMOS technology. And a multiplication ratio of MN / (N+k) can be obtained, in which M, N and K are programmable. The DLL achieves around -42dB reference spur level.

Additional Metadata
Keywords delay-locked loop, digital-to-phase converter, fractional-N frequency synthesizer
Persistent URL dx.doi.org/10.1109/CCECE.2012.6334833
Conference 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012
Citation
Guo, H, & Kwasniewski, T. (2012). A DLL-based fractional-N frequency synthesizer with a programmable injection clock. Presented at the 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2012. doi:10.1109/CCECE.2012.6334833