Stray-insensitive pipelined Digital-to-Analog Converters (DACs) can be implemented without an opamp in each stage. The quasi-passive circuit designed in this method dissipates less power, runs faster, has better accuracy, and takes less area than the conventional stray-insensitive architecture. A pipelined DAC designed with a differential bipolar architecture achieves close to 13 bits of linearity at 17.664 MSps conversion rate, which makes it suitable for full-rate downstream DSL signals. The converter is designed in a 0.6-μ double-poly CMOS technology and dissipates 43 mW.

Additional Metadata
Conference 28th European Solid-State Circuits Conference, ESSCIRC 2002
Moussavi, M. (Mohsen), Mason, R, & Plett, C. (2002). A differential bipolar stray-insensitive quasi-passive pipelined digital-to-analog converter with 17.664 MSps sample rate and -85dB THD. Presented at the 28th European Solid-State Circuits Conference, ESSCIRC 2002.