The lock-in speed is an important performance criterion for ranking a frequency synthesizer, especially in wireless applications where the acquisition speed of the synthesizer determines how fast the communication can be switched from one channel to another or from off state to on. A novel fractional-N Phase Locked Loop (PLL) featuring fast acquisition and wide tuning range is proposed in this paper. The proposed method was verified in Simulink simulation.

Additional Metadata
Persistent URL dx.doi.org/10.1109/ICSICT.2012.6466718
Conference 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Citation
He, C. (Chao), & Kwasniewski, T. (2012). A fast-lock PLL with over-tuning control. Presented at the 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012. doi:10.1109/ICSICT.2012.6466718