As circuit sizes increase, a means to improve the performance of simulations is constantly demanded, without sacrificing the accuracy of the results. To achieve this goal, a new parallel scheduler is presented exploiting binary link formulations that allows modern multi-core processors to achieve superior performance. These improvements are obtained without sacrificing accuracy or resorting to iterative techniques.

Additional Metadata
Persistent URL dx.doi.org/10.1109/LASCAS.2013.6519091
Conference 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013
Citation
Paul, D., Achar, R, Nakhla, M.S, & Nakhla, N.M. (2013). Efficient parallel scheduler for circuit simulation exploiting binary link formulations. In 2013 IEEE 4th Latin American Symposium on Circuits and Systems, LASCAS 2013 - Conference Proceedings. doi:10.1109/LASCAS.2013.6519091