The effect of rapid thermal anneal cycles typical of those required for source/drain implant activation on flatband voltage, interface state density, and dielectric strength in MOS capacitors with heavily in-situ boron doped polysilicon gates over thin thermal oxide is studied. Anneal cycles of up to 1050°C, 10 s should be acceptable for use of in-situ doped p+ gates in a CMOS process.

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Conference 24th European Solid State Device Research Conference, ESSDERC 1994
Citation
Dantu, S.V., Tarr, N.G, & Peters, C.J. (1994). In-situ doped P+ polysilicon as a MOS gate material. Presented at the 24th European Solid State Device Research Conference, ESSDERC 1994.