Clock synchronization in many protocols such as IEEE 1588 is achieved by exchanging timing information between a master and slave node. Packet delay variation (PDV) is a major source of inaccuracy in packet-based synchronization systems. When the expected values of the delays from master to slave and from slave to master are not equal, the synchronization problem can be modeled as a biased estimation problem. In this paper we propose a solution to estimate the delay bias and use this estimate to improve the synchronization accuracy. Our method is easy to implement and is compatible with the current version of the protocol. Moreover, this method allows us to update the slave clock recursively rather than after collecting many samples. The proposed method works well in the presence of frequency offset and does not require any assumption on the filter which is used in the synchronization process.

Additional Metadata
Keywords asymmetric delays, Boot-strap method, IEEE 1588, two-way message exchange mechanism
Persistent URL dx.doi.org/10.1109/ISPCS.2014.6948530
Conference 2014 8th International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication, ISPCS 2014
Citation
Hajikhani, M. (Mohammadjavad), Kunz, T, & Schwartz, H.M. (2014). A recursive method for bias estimation in asymmetric packet-based networks. Presented at the 2014 8th International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication, ISPCS 2014. doi:10.1109/ISPCS.2014.6948530