Additional Metadata
Keywords Backplane, Equalizer, Finite-impulse-response(FIR), Group delay, Inter-symbol-interference(ISI)
Persistent URL dx.doi.org/10.3969/j.issn.0372-2112.2014.11.025
Journal Tien Tzu Hsueh Pao/Acta Electronica Sinica
Citation
Zhu, X.-D. (Xu-Dong), Chen, D.-Y. (Dian-Yong), & Kwasniewski, T. (2014). A CMOS high-speed backplane transmitter with 4 reconfigurable equalization schemes. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 42(11), 2291–2297. doi:10.3969/j.issn.0372-2112.2014.11.025