All-digital bang-bang phase-locked-loops suffer from unwanted output spurs due to their non-linear behavior. The digital implementation of these PLLs often introduces extra delay which affects the performance of BBPLLs. This comes from the retiming and resampling of the digital data in the loop. In this work the phase detector hysteresis is investigated as a source for additional performance degradation. The jitter dependency on the loop parameters in the presence of hysteresis is analyzed, providing a new insight to be considered when designing for minimum jitter. This analysis provides a quick estimation of the deterministic jitter and the location of the spurious tones thus allowing the timing resolution of the PD to be determined. A new model for the BBPLL is also introduced that considers the non-ideality of the PD and its effect on the loop. To evaluate the performance, a time-amplifier is used to improve the resolution of the PD. Jitter and spurious tone of the BBPLL with TA assisted PD are then compared with those of a loop with a regular PD. The results show that the TAPD improves the performance by a factor of 3. The design and simulations have been done in a 32-nm CMOS technology.

Additional Metadata
Keywords All-digital PLLs, bang-bang PLL, jitter, limit cycles, spurious tones, time amplifier
Persistent URL dx.doi.org/10.1109/TCSI.2014.2365871
Journal IEEE Transactions on Circuits and Systems I: Regular Papers
Citation
Bashiri, S. (Samira), Aouini, S. (Sadok), Ben-Hamida, N. (Naim), & Plett, C. (2015). Analysis and modeling of the phase detector hysteresis in bang-bang PLLs. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(2), 347–355. doi:10.1109/TCSI.2014.2365871