This letter presents a reduced reference spur multiplying delay-locked loop (MDLL). The static phase offset (SPO) between the reference edge and its counterpart of MDLL output is the dominant mechanism causing reference spur in the spectrum of MDLL output. SPO is mainly caused by the non-idealities on charge pump (e.g., sink and source current mismatch) and control line (e.g., gate leakage of loop filter and voltage-controlled delay line control circuit). With a high-gain stage inserting between phase detector/phase frequency detector and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. To validate the effectiveness of the proposed technique, an MDLL is implemented in TSMC CMOS 0.18μm process. The simulation result shows that -60.1dBc reference spur was achieved at center frequency of 1.8GHz.

Additional Metadata
Keywords Delta modulator, Deterministic jitter, Multiplying delay-locked loop, Reference spur, Static phase offset
Persistent URL dx.doi.org/10.1002/cta.2176
Journal International Journal of Circuit Theory and Applications
Citation
Wang, Xin Jie, & Kwasniewski, T. (2016). A reduced reference spur multiplying delay-locked loop. International Journal of Circuit Theory and Applications, 44(8), 1620–1627. doi:10.1002/cta.2176