This study presents a novel SRAM architecture focused on minimizing area utilization for sub- and near-threshold operation in ultra-low power applications. This new architecture utilizes a modified 6T SRAM cell, introduces horizontal bit-lines, mitigates half-select disturb, and supports bit-interleaving. The proposed design's stability was thoroughly tested in the presence of process, temperature, and voltage variations and compared to the standard 6T and traditional 8T cells. A 32kb SRAM block implementing the proposed architecture was designed, simulated, and compared to a traditional 8T SRAM cell block. The results show that the proposed design has lower power consumption than the 8T SRAM block, comparable read performance, and better write performance. This was all achieved while only having a 10% increase in area per bit over the conventional 6T thin-cell layout.

Additional Metadata
Persistent URL dx.doi.org/10.1109/MWSCAS.2015.7282091
Conference 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
Citation
Basuta, S. (Sukneet), & Shams, M. (2015). Single-ended 6T sub-threshold SRAM with horizontal local bit-lines. Presented at the 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015. doi:10.1109/MWSCAS.2015.7282091